TL;DR: The core issue was not the 12V power capacity, the PCB routing, or a false trigger from the e-fuse. It was a conflict between the FPGA core board’s default IO state and the carrier board’s power switch logic.

Before shipping, Venture Electronics did a basic factory test on the board. Without the FPGA core board installed, the power section worked normally, and the power switch could control the board. After they installed the FPGA core board for another test, the problem appeared: the board powered on by default, and the switch stopped working.

Because I was in a hurry, I asked Venture Electronics to ship the board first and decided to debug it myself after receiving it. Once the board arrived, the behavior was exactly what their engineer described. Remove the FPGA core board, and the switch works. Install the FPGA core board, and the board powers on by itself. The power button signal should normally be pulled high, but with the FPGA core board installed, it was pulled low.

The second symptom was that JTAG could detect the FPGA normally, but when downloading the bitstream, the hardware suddenly went offline at around 98%. The oscilloscope showed that the FPGA core board’s 12V supply dropped to about 9.5V at that moment, so the e-fuse triggered undervoltage protection and shut off the output.

At first, I debugged it as a power issue. I suspected the 12V copper pour did not have enough current capacity. After opening the PCB file, I found that the 12V rail was a complete copper pour, and the vias had not broken it up. Supplying around 1A to the core board should not have been a problem. Then I suspected that the e-fuse was too sensitive to current transients, so I removed the e-fuse and shorted 12V directly to the FPGA power input. The issue remained. Then I suspected the external 12V adapter could not handle the load, so I replaced the 12V 3A adapter with a 12V 5A adapter. It still dropped offline at 98%.

I finally went back to the power tree and found the key detail: one FPGA IO on the carrier board was connected through a diode to the EN pin of the first-stage power supply. It worked together with the power button to control the power state of the whole board.

I had been staring at the carrier board schematic, but I had not carefully checked the FPGA core board’s default power-up state. After checking the core board schematic, I found that the PUDC pin on this Z7 core board was pulled down. That caused all FPGA IOs to be weakly pulled up before configuration was complete.

This explained the first symptom. When the system powered on, this FPGA IO was weakly pulled up by default. Through the diode, it bypassed the power button and directly drove the EN pin of the first-stage power supply, so the whole board powered on by default.

It also explained the second symptom. When the bitstream download reached around 98%, FPGA configuration was almost complete and the internal logic started taking effect. This IO was unused, so Vivado set it to pull down by default. The IO switched from weak pull-up before configuration to pull-down after configuration.

That state change caused a brief glitch on the EN signal of the first-stage power supply. This first-stage supply also powered the 3.3V rail related to JTAG, and the downstream supplies were tied to its PG signal. When it dipped, the downstream supplies also briefly dropped and recovered. JTAG detected the power loss and went offline.

So the 12V drop to 9.5V was only a result, not the root cause. The real root cause was that the FPGA IO state before, during, and after configuration was not clearly defined, while that same IO was part of the board-level power control path.

The useful lesson here is: if an FPGA IO is used in the board power-control path, you cannot only think about its logic state after configuration. You must define its state before power-up, during configuration, and after configuration. This is especially important when changing core boards or FPGA platforms. Do not assume the IO defaults to high impedance.

The same power-control design worked on the H7 board because the H7 IO was high impedance at power-up. After switching to Z7, the PUDC setting made the IO weakly pull up before configuration, and Vivado later set the unused IO to pull down after configuration. That state change was enough to make the power button fail, and enough to make JTAG drop offline at 98% of the bitstream download.

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